1. Field of the Invention
The present invention relates generally to a semiconductor device and, more specifically, it relates to a semiconductor device formed on a semiconductor substrate with a trench, in which the generation of the stress can be prevented at the corner portion where the bottom surface and the sidewall surfaces of the trench intersect with each other.
2. Description of the Prior Art
A dynamic type semiconductor memory device is an example of the semiconductor device formed on a semiconductor substrate with a trench. In the following, the description will be made of this dynamic type semiconductor memory device as an example.
The dynamic type semiconductor memory device has been well known. FIG. 1 is a block diagram showing the whole structure of such conventional dynamic type semiconductor memory device.
Referring to FIG. 1, the dynamic type semiconductor memory device comprises an array including a plurality of memory cells serving as a memory portion, a X decoder and a Y decoder for selecting the address, and input/output interface portion including a sense amplifier connected to an input/output buffer. Each of the memory cells is connected to each intersection of a word line connected to the X decoder and a bit line connected to the Y decoder, with the word line and the bit line constituting a matrix. The said array is thus structured.
The operation will be hereinafter described. Upon receipt of externally applied row address signal and column address signal, a memory cell is selected which is at the intersection of one word line and one bit line selected by the X decoder and the Y decoder, and the information is read from or written to the memory cell through the input/output interface portion including the sense amplifier and through the input/output buffer.
FIG. 2 is a cross sectional view of the above described one memory cell. The memory cell comprises a capacitor for storing information carrying charge and a transistor for reading and writing the information carrying charge.
Referring to FIG. 2, the capacitor comprises an impurity diffusion layer 8 formed on the sidewalls of the trench 25 of the semiconductor substrate with a trench 25, and a capacitor plate electrode 10 formed thereon with a dielectric film 9 interposed therebetween. The transistor comprises impurity diffusion layers 13a and 13b formed on a main surface of the semiconductor substrate 1 spaced apart from each other and a transfer gate electrode 12 (word line) formed on that portion of the main surface of the semiconductor substrate which is sandwiched by the impurity diffusion layers 13a and 13b (channel region 26) with an insulating film interposed therebetween. The adjacent two memory cells are separated from each other by a region 6 for isolation between devices formed on the bottom portion of the trench 25. The impurity diffusion layer 13a is connected to an impurity diffusion layer 8 of the capacitor formed on the sidewalls of the trench 25 of the semiconductor substrate. The impurity diffusion layer 13b is connected to an aluminum wiring 15 which is to be the bit line. The bit line is separated from the word line or the like by an interlayer insulating film 14. A surface protection film 16 is formed on the bit line.
The data writing/reading operation of the memory cell will be described with reference to FIG. 2. In writing data, when a prescribed potential is applied to the word line 12, an inversion layer is formed in the channel region 26, so that the channel region 26 becomes conductive. Therefore, the charge from the bit line 15 is stored in the impurity diffusion layer 8 through the channel region 26. On the contrary, in reading data, the charge stored in the impurity diffusion layer 8 is taken out through the channel region 26 which is inverted by the application of a prescribed potential on the word line 12 and through the impurity diffusion layers 13a and 13b and the bit line 15.
The method for making a trench in a conventional semiconductor memory device shown in FIG. 2 is disclosed in, for example, "Peripheral Capacitor Cell with Fully Recessed Isolation for Megabit DRAM" K. Tsukamoto et al, Extended Abstracts of the 18th Conference on Solid State Devices and Material, 1986. FIGS. 3A to 3C are cross sectional views showing the method for making the trench disclosed therein step by step.
First, a trench 25 is formed on the semiconductor substrate 1. The portion where the bottom surface 25a and a sidewall surfaces 25b of the trench 25 intersect is processed to have a right angle (FIG. 3A).
Thereafter, a silicon oxide film 2 and a silicon nitride film 3 are formed on the main surface of the substrate 1 and on the sidewall surface 25b of the trench 25 so as to form a selective oxide film on the bottom surface 25a of the trench 25 (FIG. 3B).
The substrate is oxidized and a region 6 for isolation between devices is formed on the bottom portion of the trench 25. The silicon oxide film 2 and the silicon nitride film 3 are removed. An impurity diffusion layer 8 is formed on the sidewall surface 25b of the trench 25 and the flap surface portion by ion implantation method and the like (FIG. 3C).
Referring to FIG. 3C, a bird's beak 6a is formed at the end portion of the region for isolation between devices. The bird's beak 6a extends, with the direction of the extension changed from horizontal to vertical at the corner portion of the trench 25. Thereafter capacitor plate electrodes and so on are formed. Consequently, a trench type memory cell such as shown in FIG. 2 is provided.
As shown in FIG. 3A, the corner portion of the trench of the conventional semiconductor memory device having trench type memory cells is formed to have a right angle. When a selective oxide film is formed on the bottom surface 25a of the trench 25, the extension of the bird's beak 6a at the end portion of the selective oxide film is suppressed. The reason for this is that the silicon nitride film is hard to be lifted since the direction of the bird's beak extension changed from the horizontal direction to the vertical direction. Consequently, a stress occurs at the corner portion 25c of the trench formed on the single crystal silicon substrate 1, causing a distortion of the crystal lattice at this portion. A leak occurs at the p-n junction formed by the semiconductor substrate 1 and the impurity diffusion layer 8. Therefore, when this trench is applied to the above described dynamic RAM, the refresh for the dynamic RAM should be carried out with intervals shorter than the normal intervals.